The inventive concepts disclosed herein generally relate to Delay-Locked Loop (DLL) circuits and to electronic device including the DLL.
A DLL circuit of an electronic system may be utilized to receive an external clock signal (supplied from external the electronic system) and to generate an output clock signal in synchronization with the external clock signal. The output clock signal generated by the DLL circuit may be used as an internal clock signal in the electronic system.
The electronic system may, for example, be a semiconductor memory device. In order to secure a maximum timing margin of a memory device that uses an output clock signal generated by a DLL circuit as an internal clock signal, the duty ratio of the output clock signal should be maintained at a constant level, e.g., 50%.
Generally, a DLL circuit includes a delay line composed of a plurality of delay cells, e.g., a plurality of inverters. If a duty skew occurs in the external clock signal supplied to the DLL circuit, then the duty skew is accumulated while the external clock signal is sequentially supplied to the plurality of delay cells. This can prevent the duty ratio of the output clock signal from being maintained at a constant level. Further, as the operating frequency of the DLL circuit becomes higher, this phenomenon becomes more serious and can cause malfunctioning of the electronic system (or memory device).